The present invention relates generally to the fabrication and structure of a semiconductor device for ESD protection of electronic circuit devices and more particularly to a continuous emitter bipolar device with improved ESD circuit protection characteristics.
Because of high input impedance and thin oxide gate structures, the problem of Electrostatic Discharge (ESD) damage with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits as shown in FIG. 3 which allows the ESD current to be shunted to ground. Another important characteristic of the ESD protection device is that it must not interfere with the operation of the devices it is designed to protect, while at the same time providing good protection when abnormal or ESD voltage incidents occur. Typical ESD protection devices consist of a n channel metal oxide semiconductor (NMOS) with an associated lateral parasitic npn bipolar transistor. Once triggered by an ESD incident, the device operates in the lateral npn mode to pass the high current. However, a vertical bipolar npn structure has better power dissipation capability than the NMOS, and is frequently used to provide ESD protection for the internal circuits.
ESD efficiency is typically measured by dividing the ESD xe2x80x9cthresholdxe2x80x9d voltage by the area of the ESD protection device as described in the report by Chen et al., xe2x80x9cDesign and Layout of High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits.xe2x80x9d, IIIE Journal, 1996 0-7803-2753-5/96, pp. 227 to 232. ESD threshold can be correlated to the secondary breakdown characteristic of the bipolar transistor as depicted in FIG. 1. The initial collector base breakdown (Bvcbo) initiates the device turn on which is followed by breakdown of collector to emitter (BVceo) as conduction enters the avalanche region between BVceo and Vt2, It2. Vt2 and It2 define the beginning of the secondary breakdown region in which the npn can be damaged due to Joule heating of the collector base junction. The higher the It2, that is the current threshold prior to secondary breakdown, the higher the ESD threshold, the better the ESD characteristics of the device. It is found that an increase in It2 and hence ESD threshold, scales with emitter length. However, as emitter length is increased there is a corresponding increase in device area. This takes up valuable active circuit area, and results in increased device capacitance which is detrimental in high speed circuit operation. In an effort to control or reduce ESD device area while maintaining or improving ESD efficiency, prior art designs have used multiple emitter finger designs. The top view horizontal layout of one such design is depicted in FIG. 4. It is seen in FIG. 4 that there are N+1 base conductors 20 for every N emitter fingers 28. In the case shown, N=4 and therefore there are 5 base connections 20 running in a horizontal interdigitated fashion between the emitter fingers 28.
The schematic of FIG. 3 shows a simplified equivalent circuit of the device with the collectors 18 electrically tied together 34 and to the input pad 40. The bases 20 are tied to the emitters 28 through the base spreading resistance 38 depicted as resistors Rb1, Rb2, Rb3, and Rb4 and additional conductor elements 32. Typically the base and emitter elements are then connected to ground 30. The objective of the prior art layout is to optimize the design to make the base resistance as equal as possible (Rb1=Rb2=Rb3=Rb4) so that the emitters will turn on uniformly at the same time to conduct the ESD current. However, there are still four different emitter fingers 28 in FIG. 4 in which process variation can cause slight differences in electrical characteristics as well as in the characteristics of the base elements. This design structure therefore cannot always assure turn-on of all the emitter base elements to maximize the device ESD current capability.
It is desired to find a manufacturing method and device structure that maintains or improves the ESD efficiency of the multi emitter finger device with improved turn on characteristics and resistance to ESD damage.
U.S. Pat. No. 5,850,095 issued to Chen et al., describes an electrostatic discharge (ESD) protection circuit with a different emitter layout and structure from that described by the invention
U.S. Pat. No. 5,341,005 issued to Canclini shows different structures for ESD protection.
U.S. Pat. No. 5,528,189 issued to Khatibzadeh., shows an amplifier with ESD protection with emitter finger layouts.
The following technical report previously referenced also refers to the subject of ESD protection.
xe2x80x9cDesign and Layout of High ESD Performance Circuits, IEEE, 1996 0-7803-2753-5/96 pp. 227 to 232. The report discusses various ESD protection device layouts.
Accordingly, it is the primary objective of the invention to provide an effective and manufacturable method and structure for improving semiconductor device resistance to the potential damage caused by the phenomenon known as electrostatic discharge (ESD) by utilizing a vertical bipolar npn transistor structure.
It is a further objective of the invention to improve ESD protection by providing a structure with higher ESD efficiency and be less susceptible to ESD damage.
Yet another objective of the invention is to provide a structure with improved ESD efficiency while at the same time maintaining or reducing structure size and capacitance which will enable reduced chip size and improved high speed performance.
A still additional objective of the invention is to provide the improved ESD protection without changing the characteristics of the internal circuits being protected and by using a process compatible with the process of integrated MOS device manufacturing.
The above objectives are achieved in accordance with the methods and structures of the invention which describes an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency and a manufacturing method for the device. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in a npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with a unique emitter design layout structure. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations on the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.